Self-organized neural network for the quality control of 12-lead ECG signals

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En binare signalent present invention has for object a method and transcoding devices of binary information for transmission time multiplex.

Conventionally raised particularly in the chapter 2. Indeed, conventionally it is desired to avoid the establishment of specific transmission clock signal connections and synchronization as soon as the transmission lengths are no en binare signalent negligible.

Thus EP-A discloses a method and apparatus for reducing jitter when transcoding block of digital signals en binare signalent are applied en binare signalent transcoded signals for en binare signalent binary data for three ternary data and vice versa.

Simultaneously we try to compress the bandwidth overall transmitted signals to facilitate transmission and therefore a correct reproduction of the information. Often also seeks to eliminate the DC component of the spectrum of the transmitted signals in order to electrically isolate the transmission links in relation to equipment which en binare signalent connect.

This led to search for transmission codes with the best possible compromise based on the requirements, such HDB3 code conventionally used for external time-division multiplex transmission of information initially encoded binary NRZ to and from external junction terminals many of temporal switching networks.

An additional requirement conventionally not obtained with the conventional time-division multiplex transmissions is that the whole of the nominal flow of a link is assigned to the transmission of binary information received by the equipment sending them. For example the frame of primary PCM multiplex transmissions to assign that thirty of the thirty two channels for the transmission of binary information to user requirements, since en binare signalent remaining channels are used for signaling and synchronization.

If this is an acceptable disadvantage when the number of time slots inaccessible to users is low relative to the number of en binare signalent channels, it is even more en binare signalent otherwise. But it is sometimes necessary to have temporal connections comprising only a very small number of channels, for example in the time private central multiservice type comprising notably slow remote equipment. US-A-4 proposes a binary information transcoding system including time-division multiplex transmission which enables one hand the reconstruction of binary data after transmission, on the other hand the transmission of additional indications, such indications en binare signalent or synchronization, while retaining the same binary information flow in the presence or absence of additional indications.

In such a system, it is important that the sequence of ternary elements belonging to groups not transmitting additional indication can forfuitement imitate a group transmitting a further indication for example a framing indication to be accidentally emulated.

To make the present invention provides a method and trancodage devices for time-division multiplex transmission to eliminate these risks. According to another feature of the invention the decoder means comprises: Conventional manner time-division multiplex transmission that includes a transmission encoder device 1, receiving binarizing DB information to be transmitted multiplexed in time with each other and optionally with IF signals also in binary form.

The set of binary data comprising this information and these signals typically arrive at the timing of signals of a non represented H clock which is assigned for example to the body to which the encoder en binare signalent 1 is assigned.

Further guidance VT are also provided under the control of en binare signalent clock for example to allow the return of information and signals after transmission, the additional indications are en binare signalent VT frame locks or possibly labels signaling the start and possibly the end for specific information or signaling.

The encoder device 1 as shown in Figure 1, is connected to a transmission 2 by way link on which it transmits in pulse en binare signalent, to a receiving decoder 3. In the example shown the transmission 2 binding is symbolized by a conventional wire bond to which the encoding device 1 and decoding device 3 are connected via input transformers 4 and Release 5 which provide on the one hand transmission of pulses of the en binare signalent device to the link and secondly to the connection to the decoder device.

Of course according to a usual practice the transmission link 2 may be associated with an opposite direction transmission link for simultaneous bidirectional exchanges, it can also serve one or more encoders emission devices operating alternately in relation to one or more decoders devices reception.

According to a conventional technique, binary signals constituting the information and signals to be transmitted is transcoded at the encoder device 1 in order to best satisfy the objectives of transmission that one is fixed and they are transcoded in opposite direction at the decoder device 2 so as to be output in binary form for operational requirements. According to a first aim, already mentioned above, according to the invention it is sought to simultaneously transmit the binary data constituting the En binare signalent information, the IF signals, the M transmit clock signals and the additional guidance VT.

This is obtained at the encoder en binare signalent 1 by a binary-binary transcoder 6 associated with a binary-ternary converter 7. At the decoder device 3, a binary-binary transcoder 11 in series with a ternary-binary converter 8 in the transmission link 2 Release can reconstruct the DB information and the IF signals.

A clock recovery circuit 9 placed in parallel with the ternary-binary converter 8 in conjunction Release 2 provides HR en binare signalent signals corresponding to the H clock signal used in transmission by the encoder device 1 it controls the binary-binary transcoder A control circuit 10 is also placed at the output of the ternary-binary converter 8 in order to control and exploit the additional information transmitted VT, it receives timing signals from the clock recovery circuit 9.

As noted above, we try to book the largest possible part of the transmission channel that en binare signalent the connection for 2 binary information DB to be transmitted and this regardless of the size of the channel. Thus in the case of time-division multiplex 2 transmissions included in a time division switching system not shown including channels of different sizes ranging for example from four to one hundred twenty eight channels per frame one tries to reserve as many channels and 'channel time intervals binary traffic information DB.

This may involve for example a transmission of signals as messages to release for general use time slots of a channel provided for signaling in the absence of such signs. According to the invention comprises the successive binary data to transmit four by four, which is usually no problem because the binary information and signals are often composed of bytes or nibbles or multiples of these bytes or nibbles such en binare signalent this is especially the coded speech signals or PCM signals by the quartet PCM time division switching systems according to the CCITT G review.

Each group of four binary data thus corresponding to two combinations of four ternary values, one of the combinations is associated with the addition of a further en binare signalent indication with respect to each other. Can thus be transmitted by selecting a combination or the other is a group, or the group plus an extra indication while using in each case only four ternary values, this additional indication VT is for example a registration indication transmitted together time that the first data of a message or DB information data to be transmitted.

All other combinations are considered abnormal and define a set CX. One can also choose according to another variant of combinations for all C2 which are very different combinations C1 by their organization. In normal operation is therefore transmits a en binare signalent of combinations belonging to the group C1 between which are inserted individually and regularly combinations belonging to the set C2, C2 each combination being normally separated from any other combination C2 by a series of C1 combinations.

In different variations we generally seeks to avoid as much possible combinations initations C2 thereafter ternary data constituting the C1 combinations at least during periods when the confusions are disruptive, particularly when the occurrence of a combination C2 is predictable or expected. In this aim in the first en binare signalent we should consider any recurrences scheduled for C2 combinations, either as for example one is dealing with a cyclical recurrence as that obtained when the additional indications are framing indications or recurrence acyclic fixed as in the case of predetermined length messages.

A simple count then checks whether there is indeed a transmission conbinaison C2 at the scheduled time and triggering a search in the absence of such a combination to such a moment.

Secondly as en binare signalent have seen at least some cases where confusion can easily be avoided, it prevents imitation combinations C2 by ternary data constituting C1 combinations around them in arranging for these ternary data can be en binare signalent ternary combinations C1 or abnormal is to say not provided among the thirty-two combinations retained.

This en binare signalent annoying that from the time the identification of combinations is lost or uncertain. The additional indication provided by this false possible combination C2 is of course also erroneous, for example when it incorrectly reports a framing.

To the extent that we can completely avoid the risk of confusion and that in particular the following combinations derived from binary information DB to be transmitted is not foreseeable at the transmission link 2, the existing possibilities we reserve certain combinations of common interest, for example, power in case of vacuum information, upstream locking loss of the link, or in en binare signalent of PCM framing.

It is arranged for example so that the ternary C1 combinations chosen for the vacuum information, locking or loss of frame alignment MIC can not have ternary data pattern can mimic a combination C2. This without ever one of the offsets can never match a combination that C2 is necessarily affected unit weight of a positive or negative sign.

Such code has the advantage of being suitable for transmission over relatively long en binare signalent due deductions combinations that lead to a significant DC component. Whatever the choice, the encoder device for en binare signalent these combinations has the important advantage simplicity as shown by the following description.

This coding device is constituted as en binare signalent above by a binary-binary transcoder 6 and a binary-ternary converter 7 inserted in series between the sources of binary Db and signaling information Si and the primary winding 13 en binare signalent the en binare signalent entry 4 of the link 2.

In this end the converter 7 comprises two shift registers 15 and 16 identical, en binare signalent type, each with its serial output connected to one of the terminals A and En binare signalent of the coil 13 via a shaping arrangement of pulse here symbolized by an amplifier circuit 17 or Shift registers 15 and 16 are clocked by the transmit clock H, they are provided for each contain a bit sequence or a zero leading respectively to emission or absence of a pulse on the terminal during each dessert H transmit clock en binare signalent provided to the read input R of each of the registers.

In this, the read-only memory 14 provides all four clock time four binary data in each of the registers 15 and 16 controlled in their goal via W. In a preferred embodiment, each group of four binary data address to one or en binare signalent other of two associations of eight binary data in read only memory 14, as the presence or absence of an additional indication to en binare signalent transmitted.

The eight bit data association are divided into two groups of four data and these groups are simultaneously transmitted in parallel to the two registers 15 and 16 for issuance. For this, the read-only memory 14 contains thirty-two individually addressable groups of eight binary data, these thirty two associations are divided into two groups of six and each group corresponds to one of two sets of sixteen ternary combinations C1 or C2.

The decoder device 2 Figure 3 is also of simple construction, it comprises two conventional circuits 21, 22 for shaping the signals received which are placed across the secondary 20 'of the output transformer 5. These shaping circuits 21, 22 feeds the clock recovery circuit 9 which conventionally takes advantage of the transitions of the output of the shaping circuit signals to en binare signalent a en binare signalent signal reproducing the reconstituted clock signals having a governed the emission by the coder device 1 as mentioned above.

Fitness circuit 21 and 22 also feed two register units 23 and 24 of the ternary-binary converter 8 which each recorded signal level at the output of a shaping circuit of the rhythm HR recovered clock.

Each register unit comprises for example a first register series and parallel outputs 25 and 26 input, en binare signalent input of each of these registers is connected to the output of a fitness circuit 21 and 22 and each of outputs are connected to the input terminals en binare signalent a second register 27 or 28 of the type with parallel inputs and outputs.

The outputs of registers 27 and 28 are connected to as many inputs of a decoder 29 providing the addressing of a read-only memory 31 in the binary-binary transcoder This read-only memory 31 en binare signalent outputs type three states and it has only thirty two lines corresponding to the selected thirty two combinations that are only likely to activate.

Each line comprises a group of four binary data, and a C1 or VT indication of all C1 or C2 combinations allowing its addressing.

At each address by eight bits simultaneously supplied by the registers 27, 28 thus corresponds to either the parallel transmission of four bit data from the memory 31 to a transmit register 32 if the address en binare signalent is one of the thirty-two en binare signalent provided or an indication CX decoder output 29 if the address combination is different.

In order eight bits provided by the two second registers en binare signalent, 28 all four HR clock time are applied to a compaction die incorporated in the decoder 31 which en binare signalent a en binare signalent of five bits to serve for the addressing of lines of the read-only memory 31 which provide an indication CX possibly associated with additional information not listed here.

En binare signalent and VT indications are provided with the binary data D in the memory output 31 and an indication of abnormality CX allows to report any combination of abnormal addressing, that is to say not en binare signalent the thirty-two combinations en binare signalent.

The VT indication is provided to a controller PLC 33 of control circuit 10, it is combined with an internal locking information TO provided by an up-down counter 34 which receives an indication of the clock recovery circuit 9 every "m "clock time" m "is selected equal to four in the example chosen or frame has four tracks and where there is a frame locking all four lanes.

The CX signal is used to change the playing time of the registers 27 and 28 in case of bad timing. The various operations performed by the decoding device 3 and with different states are symbolized by the diagram presented Figure 4 for a system in which this is a temporal framing indication that constitutes the additional VT indication transmitted by the coding quartets using combinations selected from the group C2.

The first best binary options signal trading platform providers oacom necessary to the operation of decoder device 3 at the start of transmission is the lock mark corresponding to a reference state "0" in Figure 4, it must allow to properly decode the data received subsequently.

The decisive factor is en binare signalent a combination of all C2 by the transcoder 11 via the registers 23 and A setting such a combination C2-up of the connection is typically used for the first nibble transmitted and therefore can synchronize immediately the decoder 3, it results in the appearance of a VT signal memory output a read-only The transcoder 11 then performs the pre-positioning of the down counter 34 to its initial position for counting a time equal to the duration of a frame to the end of which it will issue an internal down counter latch signal TO, the pre-positioning is ensured by a signal PR of the control PLC This causes the passage en binare signalent the decoder 3 of the search condition to a device engaged state referenced 1 in Figure 4 for which any transmission of the received data to the receiving member is blocked by absence of signal VR as well as in the "0" precedent.

From this "1" state, the normally determinants are the receipt of a second combination of identical or different C2 value, simultaneously with an internal locking TO signal provided by the down counter The state is then reached a synchronism state referenced "2" in Figure 4. Another determining factor from state "1" is receiving a combination C2 prior to the lapse of a frame from the previous combination C2, that is to say, before receiving a locking internal frame TO.

This indicates that one of the two combinations C2 successively received is imitated and is arbitrarily considered that the last received combination is correct by repositioning the down counter 34 to the initial position via the RA signal and receipt of signal VT, by returning to the decision "1", for further proceedings.

A further determining factor from state 1 en binare signalent the reception of an internal framing TO before receiving en binare signalent combination C2. This leads to a return to baseline research referenced "0" since the combination C2 having previously led to the "1" was probably an imitation due to bad timing. The en binare signalent of a combination of all CX is also a key element from the engaged state "1" insofar as it reflects a lack of transmission or coding the decoder 29 knows differentiate it leads a return to the state of search "0", with an offset which is for example three bits in each set of registers 23, 24 en binare signalent the control signal X.

Note also the ability to search by setting reset information RZI served by the body, this opportunity will not be developed further here. When the synchronization has been established state "2"the decisive factor is receiving a En binare signalent internal framing that triggers en binare signalent verification simultaneous existence or coincidence of a C2 combination resulted in the presence of a VT signal at the control automaton If such a en binare signalent is there issue a recovered lock signal VR to the en binare signalent register to confirm the issue and a new repositioning PR signal to the initial counting state of the down counter The controller remains the synchronized state "2".

If the coincidence does not occur, there is issue of VR and PR signals, the controller switches to a control state "3" in which it normally waits reception of a second TO internal framing for a new check once coincidence with a combination C2. If this coincidence occurs the En binare signalent returns to its synchronized state "2" and outputs the RV and PR signals, in case otherwise the PLC will return to its initial en binare signalent of search sync "0".

Kind code of ref document: Country of ref document: Date of ref document: Year of fee payment: Ref legal event code: Figure 1 shows a block diagram, partial, of a time-division multiplex transmission for the en binare signalent of the transcoding method according to the invention. Figure 3 shows the diagram of a decoder device according to the invention. Figure 4 shows a representative diagram of the operation of a decoder device according to the invention. A decoding device for implementing the method according to claim 1, characterized in that it comprises: A decoder device according to claim 2, characterized in that the ternary-binary converter 8 is composed of en binare signalent register units 24, 25 respectively inserted between one terminal of the secondary winding en binare signalent an output transformer 5 in the transmission link 2 and the binary-binary transcoder 11 in such a manner that each of them supplies in groups of four the data which they receive at a rhythm given by the clock recovery circuit 9.

A decoder device according to claim 2, characterized in that the binary-binary transcoder 11 comprises a read-only memory 31the addressing inputs of which are connected to the output of a decoder 29 having eight inputs connected to the outputs of the register units 24, 25 in such a manner as to supply for each address either a group of four binary values DB or SI and possibly an additional indication VT or else an indication of abnormality CX. A decoder device en binare signalent to claim 2, characterized in that the control circuit 10 comprises an automatic control unit 33 and an up-down counter 34the automatic control unit receiving an internal locking information TO supplied by the up-down counter en binare signalent and the additional indication VT supplied by the binary-binary transcoder 11the up-down counter 34 receiving resetting signals PR on reception of an additional indication and the clock signals HR delivered by the clock recovery circuit 9 to its clock input.

Method and transcoding devices of binary information for transmitting time-division multiplex. Method and apparatus for transcoding binary information for time en binare signalent multiplex transmission.

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Kind code of ref document: Country of ref document: Date of ref document: Year of fee payment: Ref legal event code: Synchronous data transmission method uses a binary-binary code type MB 1C 1T wherein the data to be transmitted binarized are divided into successive blocks of M bits inverted when they have a disparity mark-space of the same sign that the already encoded data and complete by an inversion bit indicating if there was reversal and by a frame bit consisting of a parity bit for retrieving decoding cutting block coding performed.

The figure shows an encoder with input demultiplexer 10 carrying the cutting block, followed by calculation circuits of the digital sum word and parity 15 and the running digital sum 16 , with a circuit inversion 21 which processes the blocks from multiplexer 10 and parity bit under control of an inversion decision circuit 19 and a multiplexer 22 transforming into a sequence isochronous the coded binary signal from the inverter circuit 21 and complemented by a frame bit.

The present invention relates to synchronous data transmission at very high flow in particular by optical fiber links.

In a data transmission link, the data is transmitted as a sequence of isochronous symbols having no energy continuously and little low-frequency energy to simplify the control of the level of the emission sources and the gain of the receivers as well as the equalizer, and to enable transmission by the same support service and remote channels handled by separate equipment in the terminals and intermediate points of regeneration.

This sequence of symbols is generated from data using a redundant code to transmit information on the pace of symbols necessary for their recovery and quality of transmission. In the case of optical fiber links is preferably adopted a line signal to two binary levels due to non-linearities of the optical source and its temperature dependence. The binary-binary code used is generally a block code such nBmB several alphabets and bounded digital sum which converts blocks of n bits into blocks of m bits, m being greater than n, in such a manner that the difference between the numbers of ones and zeros or marks or spaces transmitted an average of zero.

Ce genre de code redondant n'utilise pas toutes les configurations possibles des blocs de m bits. This kind of redundant code does not use all the possible configurations of blocks of m bits. It eliminates the less favorable to the recovery rate and book imitable not certain configurations by a succession of bits belonging to two consecutive blocks of m bits allowed to be used for synchronization blocks.

It also allows the detection of line errors by monitoring reception of the occurrence of unauthorized blocks of m bits configurations.

Unfortunately its implementation involves a fairly complex manipulation of the bits it is difficult to achieve for very high flow rates because it reaches the speed limit operating current technologies of semiconductors. This code MB 1C has the disadvantage compared to code block nBmB several alphabets not allow recovery of synchronization blocks or error detection. One way to rotate the block synchronization problem is to precede before any reversal and transmission, each M-bit block with its inverting bit by a value of frame bit as the last bit of the block.

The present invention aims a synchronous transmission data with a code of the aforementioned kind MB 1C 1T enabling further error detection and which is of easier implementation for large transmission rates of the codes kind nBmB several alphabets. It relates to a method of synchronous data transmission wherein the transmitted symbols are generated from an encoding type MB 1C 1T having a frame bit whose value is a function of the parity of each M-bit block to be coded the number M is chosen equal to an even number.

It also relates to coding and decoding circuits implementing the aforesaid method. The frame bit allows, by reason of its definition, an error detection within each transmitted block. It further makes constant parity units formed by an M-bit block, a frame bit and an inversion bit resulting from the encoding.

This enables the block synchronization reception recovery because it distinguishes the cutting block adopted the issue among all the other possible. It also allows a control of the error rate of transmission without resuming synchronization blocks by monitoring the DC component resulting in the parity signal obtained by dividing by two the train of coded pulses received.

The definitions of parity bits and inversion are in an implementation of simplification of the coding and effectiveness of error detection. In particular it can be done according to a choice of even or odd parity that is imposed on units formed by an M-bit block, a frame bit and an inversion bit resulting coding.

Other features and advantages of the invention will become apparent from the following description of a- in embodiment given by way of example.

Cette description sera faite en regard du dessin dans lequel: This description is made to the drawing in which: It is understood however that the invention is not limited to this particular value of M. It has an input demultiplexer 10 which, under control of a time base synchronized by the 11 Fe rate of bit stream Te incident, converts it into successive blocks of 12 parallel bits available at its output.

Two logic calculation circuits 15, 16 are placed one after the demultiplexer The first 15 delivers on an output 17 the parity bit or frame coding, hereinafter referred to as P, and an output 18 the value of a digital sum SNM with sign corresponding to the block of 12 bits of the binary word formed provided at the output of demultiplexer 10 completed the parity bit P and an inversion bit C prepositioned at logic level selected to signal a non-inverted block. The second input 16 receives the digital sum word SM output from the first logic calculating circuit 15 and the signal output an inversion decision circuit 19 and provides at an output 20 the sign of the running digital sum CNS bit stream Ts generated by the encoder.

The inversion decision circuit 19 compares the signs of the digital sum SNM word and the running digital sum SKC delivered respectively by the two logic calculation circuits 15, 16 and controls an inverter circuit 21 operating on the block 12 bits available at the output of the demultiplexer 10 and the P parity bit available at the output of the first computation logic circuit Il se compose de plusieurs additionneurs binaires en cascade.

The computation logic circuit 15 is detailed in Figure 2. It consists of multiple binary adders in cascade. An incomplete adder of four binary numbers by one bit only delivering that the least significant bit of the result of the addition has its bit outputs to inputs connected to the least significant of the four adders of the first adder group and outputs the parity bit P.

A second group of two full adders , of two binary numbers of two bits added together pairwise numbers delivered by the first adder group in the presence of an order carry C indicated by a logic 1 on their carry input Ci. The parity block of 12 bits available at the output of the demultiplexer 10 is that the number of ones therein. In binary, this corresponds to the value of the most significant bit of the summation of the twelve bits of the block considered 12 independent binary numbers of one bit.

This summation is carried out in two stages, one in which the first group of adders , , , carries four partial sums y 0, y 1, y 2, Y3 three by three of the 12 bits and another in which, incomplete calculates the value of the most significant bit adder of the sum of the least significant bit y 00 'y 10 Y 30 Y 20Y of the four partial sums.

Incomplete adder may be constituted, as shown, by a cascade of three logic gates of the type "exclusive-OR" with two inputs. It generates a parity bit P at logic level 1 or 0 depending on whether the block of bit is odd or even. The word consists of bit block outputted from the demultiplexer 10 and its parity bit P is a constant even parity.

The 14 bit word consisting of bit block outputted from the demultiplexer 10, its parity bit P and the inversion bit C prepositioned at a predetermined logic level here chosen equal to a constant odd parity. This parity property is retained in a reversal because of the even number of bits. Digital sum word SNM, before any reversal is proportional to the difference between the numbers of ones and zeros in the word formed from the block of 12 bits available at the output of the demultiplexer 10, its parity bit P and its bit inversion C.

Soit x 0 ,.. S 0 is the sum performed by the last adder whose input receives the retaining parity bit P. The sum Sa output from the adder , the sum of the 15 bits of the word formed by the block of 12 bits delivered by the demultiplexer 10, the parity bit P and the two carry bits is expressed in four bits. The value of the word digital sum SNM is obtained by subtracting the value 3 to the sum S 0.

In a binary arithmetic four digit complement to two, this subtraction is done by adding so that it can be considered that the sum S 0 represents, in this arithmetic, the word digital sum with a negative sign.

The logic circuit 16 for calculating the running digital sum CNS data stream output from the encoder is detailed in Figure 3. It has been designed taking into account that the numerical sum word is issued in a binary arithmetic three digits complement to two.

This multiplier performs sign or not, on the order of decision circuit 19, a a complementation of the sum S 0 delivered by the first computation logic circuit. Each complementation to the sum S 0 a logic 1 is applied to the adder carry input to transform it into two complementation and thus achieve the sign inversion. It is noted that can be looped back on the adder itself because of the chosen coding scheme whereby a running digital sum SNC initialized to zero is within the range of variation of the digital sum word SM.

FIG 3 also shows the logic gate "or two-input exclusive of the inversion decision circuit 19 having a normal output and an inverted output One of this logic gate inputs is connected to the bit sign S 03 most significant bit of the sum S 0 delivered by the first computation logic circuit 15 while the other is connected to the output of the parallel registers on the one assigned to the most significant bit of the output the adder Figure 3 also shows the inversion circuit 21 which consists of a battery of thirteen type logic gates "XNOR" with two inputs each connected by an input to the output of the logic gate constituting the decision circuit inverting 19 and respectively receiving on the other inputs the twelve bits of the block outputted from the demultiplexer 10 and the P parity bit delivered by the first computation logic circuit Note that the choice of a blank Te incident data stream into blocks of 12 bits combined with the choice of an inversion bit having a logic level 1 to express a coding without inversion allows to calculate the word digital sum in a binary arithmetic complement four digits in pairs by a simple summation in natural binary of the number of ones included in the bit block and its parity bit increased by two units and that the selection of a parity bit transforming the bit block to which it is associated, completed the inversion bit C, in a 14 bit word of odd parity is used to calculate the running digital sum in a binary arithmetic complement three digit two.

Alternatively, one can choose an inversion bit having a logic level 0 to express a coding without inversion and calculate analogously digital sum word only by increasing by one unit the demand made in natural binary. One way to reconcile these two cases is to carry the carry input of one of the adders , to logic level 1 and the carry input of the other logic level corresponding to the inversion bit C report of a non-inverted block. The parity bit can be obtained simply on an inverting output of the adder Also as a variant, one can choose to form codewords of even parity.

The calculation of the sum digital word can be performed similarly to that described above for codewords of odd parity. For calculating the running digital sum, one can not neglect the least significant bit of the sum SO that are odd, this calculation is therefore carried out in this case, for codewords of 14 bits in a binary arithmetic either three additional figures two but four additional digits in two. The error coding this multiplier or ratio between the number of line errors and the number of errors after decoding equals: It is deduced from the fact that an error in a block of 12 bits does not cause other errors in decoding, an error on the parity bit P disappears and an error decoding on the inversion bit C 12 causes errors in decoding.

Un divis The time base 40 generates a first clock signal H s having a frequency corresponding to the flow of incident encoded data stream Ts' through a controlled oscillator in phase to transitions incident data stream Ts. This H signal s is then applied by means of a cycle stealing circuit to a divider by fourteen which firstly controls the addressing of the demultiplexer 41 and also delivers a signal whose frequency fm corresponds to the rhythm of succession of the words of 14 bits used in coding and whose rising edges are converted into Hm word clock pulses by a pulse generator Eur twelve , placed after the multiplier , provides the address control of the multiplexer The cycle stealing circuit makes it possible to conceal the application cycle of the oscillator is for example a logic gate such as "and" and so delaying the clock pulses Hm word duration a received symbol.

This changes the relative locations of the symbols in the division into bit words until the right cut. The word synchronization the recovery circuit 44 includes a parity calculating circuit receiving the parallel fourteen bits of the output of the demultiplexer 41 followed by an error quantization circuit and a resynchronization control circuit. The parity calculation circuit is not detailed because it is of conventional design.

It is made for example using a logic gate cascade style "exclusive or". The type logic "and" gate associated with the divider by N selects a word clock pulse H m every N consecutive words of 14 bits delivered by the demultiplexer This serves to repositioning of the down counter which between time count parity errors logic level 0 at the output of the parity calculation circuit translating the appearance at the output of the demultiplexer 41 of a parity word opposite to that chosen for the code words and outputs an output signal normally logic 0 passing a when the countdown reaches zero.

The pulse generator transforms the rising transitions of the output signal of the down counter into positive pulses for controlling the cycle stealing circuit the non-transmission of a cycle of oscillator so as to delay for a period equal to that of one bit of the incident stream Ts ', m H the word clock pulses determining the cutting stream received Ts' into words of 14 bits.

In addition to the type of logic "and" gate , the resynchronization control circuit comprises a D flip-flop mounted divider by two controlling by its output Q the logic gate , a down counter by presettable connected by its output to the input type of the latch clock D and two switches two-stage , cascaded to the inputs of counting and preposition of the down counter One of the selectors , is mounted inverter to the inputs downcounting and preposition of the down counter and controlled by the Q output of the D flip-flop Like the preceding down-counter, the down counter generates at its output a logic level 0 which goes to logic level 1 when the count reaches the value zero, this transition causing the change of state of the D type flip-flop Un niveau logique 0 en sortie de la bascule de type D bloque la porte logique et traduit un verrouillage de la synchronisation mot.

A logic 0 at the output of the D flip-flop blocks logic gate and reflects a lock word synchronization. A logic 1 the output of the D type flip-flop unlocks the logic gate and reflects an acquisition process of the synchronization word as a result of a loss of lock. When the synchronization word is acquired, parity is a measure of online error rate.

It may, within the scope of the invention amend certain provisions or replace certain means by equivalent means. Method for synchronous transmission of data and apparatus for its implementation. Method of and device for transmitting a digital service channel by way of the parity channel of a parity check coded digital data stream.

Method and apparatus for detecting selected absence of digital logic synchronism. DC-free line code and bit and frame synchronization for arbitrary data transmission. Encoding and decoding of dual-ported RAM parity using one shared parity tree and within one clock cycle. System for high speed serial video signal transmission using DC-balanced coding. Method and apparatus for encoding a digital signal so that it has a small DC component as well as the decoder.