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Kind code of ref document: Country of ref document: Date of ref document: Year of fee payment: Ref legal event code: Synchronous data transmission method uses a binary-binary code type MB 1C 1T wherein the data to be transmitted binarized are divided into successive blocks of M bits inverted when they have a disparity mark-space of the same sign that the already encoded data and complete by an inversion bit indicating if there was reversal and by a frame bit consisting of a parity bit for retrieving decoding cutting block coding performed.

The figure shows an encoder with input demultiplexer 10 carrying the cutting block, followed by calculation circuits of the digital sum word and parity 15 and the running digital sum 16 , with a circuit inversion 21 which processes the blocks from multiplexer 10 and parity bit under control of an inversion decision circuit 19 and a multiplexer 22 transforming into a sequence isochronous the coded binary signal from the inverter circuit 21 and complemented by a frame bit.

The present invention relates to synchronous data transmission at very high flow in particular by optical fiber links.

In a data transmission link, the data is transmitted as a sequence of isochronous symbols having no energy continuously and little low-frequency energy to simplify the control of the level of the emission sources and the gain of the receivers as well as the equalizer, and to enable transmission by the same support service and remote channels handled by separate equipment in the terminals and intermediate points of regeneration.

This sequence of symbols is generated from data using a redundant code to transmit information on the pace of symbols necessary for their recovery and quality of transmission. In the case of optical fiber links is preferably adopted a line signal to two binary levels due to non-linearities of the optical source and its temperature dependence. The binary-binary code used is generally a block code such nBmB several alphabets and bounded digital sum which converts blocks of n bits into blocks of m bits, m being greater than n, in such a manner that the difference between the numbers of ones and zeros or marks or spaces transmitted an average of zero.

Ce genre de code redondant n'utilise pas toutes les configurations possibles des blocs de m bits. This kind of redundant code does not use all the possible configurations of blocks of m bits. It eliminates the less favorable to the recovery rate and book imitable not certain configurations by a succession of bits belonging to two consecutive blocks of m bits allowed to be used for synchronization blocks.

It also allows the detection of line errors by monitoring reception of the occurrence of unauthorized blocks of m bits configurations.

Unfortunately its implementation involves a fairly complex manipulation of the bits it is difficult to achieve for very high flow rates because it reaches the speed limit operating current technologies of semiconductors. This code MB 1C has the disadvantage compared to code block nBmB several alphabets not allow recovery of synchronization blocks or error detection. One way to rotate the block synchronization problem is to precede before any reversal and transmission, each M-bit block with its inverting bit by a value of frame bit as the last bit of the block.

The present invention aims a synchronous transmission data with a code of the aforementioned kind MB 1C 1T enabling further error detection and which is of easier implementation for large transmission rates of the codes kind nBmB several alphabets. It relates to a method of synchronous data transmission wherein the transmitted symbols are generated from an encoding type MB 1C 1T having a frame bit whose value is a function of the parity of each M-bit block to be coded the number M is chosen equal to an even number.

It also relates to coding and decoding circuits implementing the aforesaid method. The frame bit allows, by reason of its definition, an error detection within each transmitted block. It further makes constant parity units formed by an M-bit block, a frame bit and an inversion bit resulting from the encoding.

This enables the block synchronization reception recovery because it distinguishes the cutting block adopted the issue among all the other possible. It also allows a control of the error rate of transmission without resuming synchronization blocks by monitoring the DC component resulting in the parity signal obtained by dividing by two the train of coded pulses received.

The definitions of parity bits and inversion are in an implementation of simplification of the coding and effectiveness of error detection. In particular it can be done according to a choice of even or odd parity that is imposed on units formed by an M-bit block, a frame bit and an inversion bit resulting coding.

Other features and advantages of the invention will become apparent from the following description of a- in embodiment given by way of example.

Cette description sera faite en regard du dessin dans lequel: This description is made to the drawing in which: It is understood however that the invention is not limited to this particular value of M. It has an input demultiplexer 10 which, under control of a time base synchronized by the 11 Fe rate of bit stream Te incident, converts it into successive blocks of 12 parallel bits available at its output.

Two logic calculation circuits 15, 16 are placed one after the demultiplexer The first 15 delivers on an output 17 the parity bit or frame coding, hereinafter referred to as P, and an output 18 the value of a digital sum SNM with sign corresponding to the block of 12 bits of the binary word formed provided at the output of demultiplexer 10 completed the parity bit P and an inversion bit C prepositioned at logic level selected to signal a non-inverted block. The second input 16 receives the digital sum word SM output from the first logic calculating circuit 15 and the signal output an inversion decision circuit 19 and provides at an output 20 the sign of the running digital sum CNS bit stream Ts generated by the encoder.

The inversion decision circuit 19 compares the signs of the digital sum SNM word and the running digital sum SKC delivered respectively by the two logic calculation circuits 15, 16 and controls an inverter circuit 21 operating on the block 12 bits available at the output of the demultiplexer 10 and the P parity bit available at the output of the first computation logic circuit Il se compose de plusieurs additionneurs binaires en cascade.

The computation logic circuit 15 is detailed in Figure 2. It consists of multiple binary adders in cascade. An incomplete adder of four binary numbers by one bit only delivering that the least significant bit of the result of the addition has its bit outputs to inputs connected to the least significant of the four adders of the first adder group and outputs the parity bit P.

A second group of two full adders , of two binary numbers of two bits added together pairwise numbers delivered by the first adder group in the presence of an order carry C indicated by a logic 1 on their carry input Ci. The parity block of 12 bits available at the output of the demultiplexer 10 is that the number of ones therein. In binary, this corresponds to the value of the most significant bit of the summation of the twelve bits of the block considered 12 independent binary numbers of one bit.

This summation is carried out in two stages, one in which the first group of adders , , , carries four partial sums y 0, y 1, y 2, Y3 three by three of the 12 bits and another in which, incomplete calculates the value of the most significant bit adder of the sum of the least significant bit y 00 'y 10 Y 30 Y 20Y of the four partial sums.

Incomplete adder may be constituted, as shown, by a cascade of three logic gates of the type "exclusive-OR" with two inputs. It generates a parity bit P at logic level 1 or 0 depending on whether the block of bit is odd or even. The word consists of bit block outputted from the demultiplexer 10 and its parity bit P is a constant even parity.

The 14 bit word consisting of bit block outputted from the demultiplexer 10, its parity bit P and the inversion bit C prepositioned at a predetermined logic level here chosen equal to a constant odd parity. This parity property is retained in a reversal because of the even number of bits. Digital sum word SNM, before any reversal is proportional to the difference between the numbers of ones and zeros in the word formed from the block of 12 bits available at the output of the demultiplexer 10, its parity bit P and its bit inversion C.

Soit x 0 ,.. S 0 is the sum performed by the last adder whose input receives the retaining parity bit P. The sum Sa output from the adder , the sum of the 15 bits of the word formed by the block of 12 bits delivered by the demultiplexer 10, the parity bit P and the two carry bits is expressed in four bits. The value of the word digital sum SNM is obtained by subtracting the value 3 to the sum S 0.

In a binary arithmetic four digit complement to two, this subtraction is done by adding so that it can be considered that the sum S 0 represents, in this arithmetic, the word digital sum with a negative sign.

The logic circuit 16 for calculating the running digital sum CNS data stream output from the encoder is detailed in Figure 3. It has been designed taking into account that the numerical sum word is issued in a binary arithmetic three digits complement to two.

This multiplier performs sign or not, on the order of decision circuit 19, a a complementation of the sum S 0 delivered by the first computation logic circuit. Each complementation to the sum S 0 a logic 1 is applied to the adder carry input to transform it into two complementation and thus achieve the sign inversion. It is noted that can be looped back on the adder itself because of the chosen coding scheme whereby a running digital sum SNC initialized to zero is within the range of variation of the digital sum word SM.

FIG 3 also shows the logic gate "or two-input exclusive of the inversion decision circuit 19 having a normal output and an inverted output One of this logic gate inputs is connected to the bit sign S 03 most significant bit of the sum S 0 delivered by the first computation logic circuit 15 while the other is connected to the output of the parallel registers on the one assigned to the most significant bit of the output the adder Figure 3 also shows the inversion circuit 21 which consists of a battery of thirteen type logic gates "XNOR" with two inputs each connected by an input to the output of the logic gate constituting the decision circuit inverting 19 and respectively receiving on the other inputs the twelve bits of the block outputted from the demultiplexer 10 and the P parity bit delivered by the first computation logic circuit Note that the choice of a blank Te incident data stream into blocks of 12 bits combined with the choice of an inversion bit having a logic level 1 to express a coding without inversion allows to calculate the word digital sum in a binary arithmetic complement four digits in pairs by a simple summation in natural binary of the number of ones included in the bit block and its parity bit increased by two units and that the selection of a parity bit transforming the bit block to which it is associated, completed the inversion bit C, in a 14 bit word of odd parity is used to calculate the running digital sum in a binary arithmetic complement three digit two.

Alternatively, one can choose an inversion bit having a logic level 0 to express a coding without inversion and calculate analogously digital sum word only by increasing by one unit the demand made in natural binary. One way to reconcile these two cases is to carry the carry input of one of the adders , to logic level 1 and the carry input of the other logic level corresponding to the inversion bit C report of a non-inverted block. The parity bit can be obtained simply on an inverting output of the adder Also as a variant, one can choose to form codewords of even parity.

The calculation of the sum digital word can be performed similarly to that described above for codewords of odd parity. For calculating the running digital sum, one can not neglect the least significant bit of the sum SO that are odd, this calculation is therefore carried out in this case, for codewords of 14 bits in a binary arithmetic either three additional figures two but four additional digits in two. The error coding this multiplier or ratio between the number of line errors and the number of errors after decoding equals: It is deduced from the fact that an error in a block of 12 bits does not cause other errors in decoding, an error on the parity bit P disappears and an error decoding on the inversion bit C 12 causes errors in decoding.

Un divis The time base 40 generates a first clock signal H s having a frequency corresponding to the flow of incident encoded data stream Ts' through a controlled oscillator in phase to transitions incident data stream Ts. This H signal s is then applied by means of a cycle stealing circuit to a divider by fourteen which firstly controls the addressing of the demultiplexer 41 and also delivers a signal whose frequency fm corresponds to the rhythm of succession of the words of 14 bits used in coding and whose rising edges are converted into Hm word clock pulses by a pulse generator Eur twelve , placed after the multiplier , provides the address control of the multiplexer The cycle stealing circuit makes it possible to conceal the application cycle of the oscillator is for example a logic gate such as "and" and so delaying the clock pulses Hm word duration a received symbol.

This changes the relative locations of the symbols in the division into bit words until the right cut. The word synchronization the recovery circuit 44 includes a parity calculating circuit receiving the parallel fourteen bits of the output of the demultiplexer 41 followed by an error quantization circuit and a resynchronization control circuit. The parity calculation circuit is not detailed because it is of conventional design.

It is made for example using a logic gate cascade style "exclusive or". The type logic "and" gate associated with the divider by N selects a word clock pulse H m every N consecutive words of 14 bits delivered by the demultiplexer This serves to repositioning of the down counter which between time count parity errors logic level 0 at the output of the parity calculation circuit translating the appearance at the output of the demultiplexer 41 of a parity word opposite to that chosen for the code words and outputs an output signal normally logic 0 passing a when the countdown reaches zero.

The pulse generator transforms the rising transitions of the output signal of the down counter into positive pulses for controlling the cycle stealing circuit the non-transmission of a cycle of oscillator so as to delay for a period equal to that of one bit of the incident stream Ts ', m H the word clock pulses determining the cutting stream received Ts' into words of 14 bits.

In addition to the type of logic "and" gate , the resynchronization control circuit comprises a D flip-flop mounted divider by two controlling by its output Q the logic gate , a down counter by presettable connected by its output to the input type of the latch clock D and two switches two-stage , cascaded to the inputs of counting and preposition of the down counter One of the selectors , is mounted inverter to the inputs downcounting and preposition of the down counter and controlled by the Q output of the D flip-flop Like the preceding down-counter, the down counter generates at its output a logic level 0 which goes to logic level 1 when the count reaches the value zero, this transition causing the change of state of the D type flip-flop Un niveau logique 0 en sortie de la bascule de type D bloque la porte logique et traduit un verrouillage de la synchronisation mot.

A logic 0 at the output of the D flip-flop blocks logic gate and reflects a lock word synchronization. A logic 1 the output of the D type flip-flop unlocks the logic gate and reflects an acquisition process of the synchronization word as a result of a loss of lock. When the synchronization word is acquired, parity is a measure of online error rate.

It may, within the scope of the invention amend certain provisions or replace certain means by equivalent means. Method for synchronous transmission of data and apparatus for its implementation. Method of and device for transmitting a digital service channel by way of the parity channel of a parity check coded digital data stream.

Method and apparatus for detecting selected absence of digital logic synchronism. DC-free line code and bit and frame synchronization for arbitrary data transmission. Encoding and decoding of dual-ported RAM parity using one shared parity tree and within one clock cycle. System for high speed serial video signal transmission using DC-balanced coding. Method and apparatus for encoding a digital signal so that it has a small DC component as well as the decoder.